common-eagle-libraries/Xilinx.lbr

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XML

<?xml version="1.0" encoding="utf-8"?>
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<eagle version="7.2.0">
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<library>
<packages>
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B
C
D
E
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G
H
J
K
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<pin name="IO_L16P_T2_35" x="-19.05" y="-16.51" length="short"/>
<pin name="IO_L16N_T2_35" x="-19.05" y="-19.05" length="short"/>
<pin name="IO_L17P_T2_35" x="-19.05" y="-21.59" length="short"/>
<pin name="IO_L17N_T2_35" x="-19.05" y="-24.13" length="short"/>
<pin name="IO_L18P_T2_35" x="-19.05" y="-26.67" length="short"/>
<pin name="IO_L18N_T2_35" x="-19.05" y="-29.21" length="short"/>
<pin name="IO_L19P_T3_35" x="-19.05" y="-31.75" length="short"/>
<pin name="IO_L19N_T3_VREF_35" x="-19.05" y="-34.29" length="short"/>
<pin name="IO_L20P_T3_35" x="-19.05" y="-36.83" length="short"/>
<pin name="IO_L20N_T3_35" x="-19.05" y="-39.37" length="short"/>
<pin name="IO_L21P_T3_DQS_35" x="-19.05" y="-41.91" length="short"/>
<pin name="IO_L21N_T3_DQS_35" x="-19.05" y="-44.45" length="short"/>
<pin name="IO_L22P_T3_35" x="-19.05" y="-46.99" length="short"/>
<pin name="IO_L22N_T3_35" x="-19.05" y="-49.53" length="short"/>
<pin name="IO_L23P_T3_35" x="-19.05" y="-52.07" length="short"/>
<pin name="IO_L23N_T3_35" x="-19.05" y="-54.61" length="short"/>
<pin name="IO_L24P_T3_35" x="-19.05" y="-57.15" length="short"/>
<pin name="IO_L24N_T3_35" x="-19.05" y="-59.69" length="short"/>
<pin name="IO_25_35" x="-19.05" y="-62.23" length="short"/>
<wire x1="-16.51" y1="63.5" x2="16.51" y2="63.5" width="0.254" layer="94"/>
<wire x1="16.51" y1="63.5" x2="16.51" y2="-63.5" width="0.254" layer="94"/>
<wire x1="16.51" y1="-63.5" x2="-16.51" y2="-63.5" width="0.254" layer="94"/>
<wire x1="-16.51" y1="-63.5" x2="-16.51" y2="63.5" width="0.254" layer="94"/>
<text x="-15.875" y="-66.04" size="1.778" layer="96">&gt;VALUE</text>
<text x="-15.875" y="64.135" size="1.778" layer="95">&gt;NAME</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="ARTIX7-256" prefix="U">
<gates>
<gate name="A" symbol="ARTIX7-256" x="33.02" y="109.22"/>
<gate name="B" symbol="ARTIX7-256-CONFIG" x="88.9" y="93.98"/>
<gate name="C" symbol="ARTIX7-256-IO14" x="33.02" y="-7.62"/>
<gate name="D" symbol="ARTIX7-256-IO15" x="88.9" y="-7.62"/>
<gate name="E" symbol="ARTIX7-256-IO34" x="132.08" y="30.48"/>
<gate name="F" symbol="ARTIX7-256-IO35" x="172.72" y="-7.62"/>
</gates>
<devices>
<device name="" package="FTBGA-256">
<connects>
<connect gate="A" pin="GND@1" pad="A1"/>
<connect gate="A" pin="GND@10" pad="F10"/>
<connect gate="A" pin="GND@11" pad="F16"/>
<connect gate="A" pin="GND@12" pad="G3"/>
<connect gate="A" pin="GND@13" pad="G9"/>
<connect gate="A" pin="GND@14" pad="G13"/>
<connect gate="A" pin="GND@15" pad="H6"/>
<connect gate="A" pin="GND@16" pad="J9"/>
<connect gate="A" pin="GND@17" pad="J11"/>
<connect gate="A" pin="GND@18" pad="K4"/>
<connect gate="A" pin="GND@19" pad="K6"/>
<connect gate="A" pin="GND@2" pad="A11"/>
<connect gate="A" pin="GND@20" pad="K14"/>
<connect gate="A" pin="GND@21" pad="L1"/>
<connect gate="A" pin="GND@22" pad="L11"/>
<connect gate="A" pin="GND@23" pad="M8"/>
<connect gate="A" pin="GND@24" pad="N5"/>
<connect gate="A" pin="GND@25" pad="N15"/>
<connect gate="A" pin="GND@26" pad="P2"/>
<connect gate="A" pin="GND@27" pad="P12"/>
<connect gate="A" pin="GND@28" pad="R9"/>
<connect gate="A" pin="GND@29" pad="T6"/>
<connect gate="A" pin="GND@3" pad="B8"/>
<connect gate="A" pin="GND@30" pad="T16"/>
<connect gate="A" pin="GND@4" pad="C5"/>
<connect gate="A" pin="GND@5" pad="C15"/>
<connect gate="A" pin="GND@6" pad="D2"/>
<connect gate="A" pin="GND@7" pad="D12"/>
<connect gate="A" pin="GND@8" pad="E9"/>
<connect gate="A" pin="GND@9" pad="F6"/>
<connect gate="A" pin="VCCAUX@1" pad="G10"/>
<connect gate="A" pin="VCCAUX@2" pad="J10"/>
<connect gate="A" pin="VCCAUX@3" pad="K11"/>
<connect gate="A" pin="VCCAUX@4" pad="L10"/>
<connect gate="A" pin="VCCBRAM@1" pad="E10"/>
<connect gate="A" pin="VCCBRAM@2" pad="F11"/>
<connect gate="A" pin="VCCINT@1" pad="F7"/>
<connect gate="A" pin="VCCINT@2" pad="F9"/>
<connect gate="A" pin="VCCINT@3" pad="G6"/>
<connect gate="A" pin="VCCINT@4" pad="H9"/>
<connect gate="A" pin="VCCINT@5" pad="J6"/>
<connect gate="A" pin="VCCINT@6" pad="K9"/>
<connect gate="A" pin="VCCINT@7" pad="L8"/>
<connect gate="A" pin="VCCO0" pad="L6"/>
<connect gate="A" pin="VCCO14@1" pad="L16"/>
<connect gate="A" pin="VCCO14@2" pad="M13"/>
<connect gate="A" pin="VCCO14@3" pad="N10"/>
<connect gate="A" pin="VCCO14@4" pad="P7"/>
<connect gate="A" pin="VCCO14@5" pad="R14"/>
<connect gate="A" pin="VCCO14@6" pad="T11"/>
<connect gate="A" pin="VCCO15@1" pad="A16"/>
<connect gate="A" pin="VCCO15@2" pad="B13"/>
<connect gate="A" pin="VCCO15@3" pad="C10"/>
<connect gate="A" pin="VCCO15@4" pad="E14"/>
<connect gate="A" pin="VCCO15@5" pad="H15"/>
<connect gate="A" pin="VCCO15@6" pad="J12"/>
<connect gate="A" pin="VCCO34@1" pad="M3"/>
<connect gate="A" pin="VCCO34@2" pad="R4"/>
<connect gate="A" pin="VCCO34@3" pad="T1"/>
<connect gate="A" pin="VCCO35@1" pad="A6"/>
<connect gate="A" pin="VCCO35@2" pad="B3"/>
<connect gate="A" pin="VCCO35@3" pad="D7"/>
<connect gate="A" pin="VCCO35@4" pad="E4"/>
<connect gate="A" pin="VCCO35@5" pad="F1"/>
<connect gate="A" pin="VCCO35@6" pad="J2"/>
<connect gate="B" pin="CCLK" pad="E8"/>
<connect gate="B" pin="CFGBVS" pad="E7"/>
<connect gate="B" pin="DONE" pad="H10"/>
<connect gate="B" pin="DX+" pad="K8"/>
<connect gate="B" pin="DX-" pad="K7"/>
<connect gate="B" pin="GNDADC" pad="G7"/>
<connect gate="B" pin="INIT_B" pad="K10"/>
<connect gate="B" pin="M0" pad="M9"/>
<connect gate="B" pin="M1" pad="M10"/>
<connect gate="B" pin="M2" pad="M11"/>
<connect gate="B" pin="PROGRAM_B" pad="L9"/>
<connect gate="B" pin="TCK" pad="L7"/>
<connect gate="B" pin="TDI" pad="N7"/>
<connect gate="B" pin="TDO" pad="N8"/>
<connect gate="B" pin="TMS" pad="M7"/>
<connect gate="B" pin="V+" pad="H8"/>
<connect gate="B" pin="V-" pad="J7"/>
<connect gate="B" pin="VCCADC" pad="G8"/>
<connect gate="B" pin="VCCBAT" pad="F8"/>
<connect gate="B" pin="VREF+" pad="J8"/>
<connect gate="B" pin="VREF-" pad="H7"/>
<connect gate="C" pin="IO_0_14" pad="K12"/>
<connect gate="C" pin="IO_25_14" pad="P6"/>
<connect gate="C" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="C" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="C" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="C" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="C" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="C" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="C" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="C" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="C" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="C" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="C" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="C" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="C" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="C" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="C" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="C" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="C" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="C" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="C" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="D" pin="IO_0_15" pad="D10"/>
<connect gate="D" pin="IO_25_15" pad="G11"/>
<connect gate="D" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="D" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="D" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="D" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="D" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="D" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="D" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="D" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="D" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="D" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="D" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="D" pin="IO_L15P_T1_DQS_15" pad="D14"/>
<connect gate="D" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="D" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="D" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="D" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="D" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="D" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="D" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="D" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="D" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="D" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="D" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="D" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="D" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="D" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="D" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="D" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="D" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="D" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="D" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="D" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="D" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="D" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="D" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="D" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="D" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="D" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="D" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="D" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="D" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="D" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="D" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="D" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="D" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="E" pin="IO_0_34" pad="L5"/>
<connect gate="E" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="E" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="E" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="E" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="E" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="E" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="E" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="E" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="E" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="E" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="E" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="E" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="E" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="E" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="E" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="E" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="E" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="E" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="E" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="F" pin="IO_0_35" pad="E6"/>
<connect gate="F" pin="IO_25_35" pad="K5"/>
<connect gate="F" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="F" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="F" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="F" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="F" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="F" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="F" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="F" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="F" pin="IO_L14N_T2_MRCC_35" pad="F3"/>
<connect gate="F" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="F" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="F" pin="IO_L15P_T2_DQS_25" pad="F2"/>
<connect gate="F" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="F" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="F" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="F" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="F" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="F" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="F" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="F" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="F" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="F" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="F" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="F" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="F" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="F" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="F" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="F" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="F" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="F" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="F" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="F" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="F" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="F" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="F" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="F" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="F" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="F" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="F" pin="IO_L5N_T0_AD13N_35\" pad="C6"/>
<connect gate="F" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="F" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="F" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="F" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="F" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="F" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="F" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="F" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="F" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="6.3" minversion="6.2.2" severity="warning">
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
</note>
</compatibility>
</eagle>