<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.4">
<drawing>
<library>
<packages>
<package name="DDR3">
</package>
<package name="TFBGA-54">
</package>
<package name="TFBGA-60">
</package>
<package name="TFBGA-84">
</package>
</packages>
<symbols>
<symbol name="SDRAM">
<pin name="VDD@1"/>
<pin name="DQ0"/>
<pin name="VDDQ@1"/>
<pin name="DQ1"/>
<pin name="DQ2"/>
<pin name="VSSQ@1"/>
<pin name="DQ3"/>
<pin name="DQ4"/>
<pin name="VDDQ@2"/>
<pin name="DQ5"/>
<pin name="DQ6"/>
<pin name="VSSQ@2"/>
<pin name="DQ7"/>
<pin name="VDD@2"/>
<pin name="DQML"/>
<pin name="!WE"/>
<pin name="!CAS"/>
<pin name="!RAS"/>
<pin name="!CS"/>
<pin name="BA0"/>
<pin name="BA1"/>
<pin name="A10/AP"/>
<pin name="A0"/>
<pin name="A1"/>
<pin name="A2"/>
<pin name="A3"/>
<pin name="VDD@3"/>
<pin name="VSS@1"/>
<pin name="A4"/>
<pin name="A5"/>
<pin name="A6"/>
<pin name="A7"/>
<pin name="A8"/>
<pin name="A9"/>
<pin name="A11"/>
<pin name="A12"/>
<pin name="CKE"/>
<pin name="CLK"/>
<pin name="DQMH"/>
<pin name="VSS@2"/>
<pin name="DQ8"/>
<pin name="VDDQ@3"/>
<pin name="DQ9"/>
<pin name="DQ10"/>
<pin name="VSSQ@3"/>
<pin name="DQ11"/>
<pin name="DQ12"/>
<pin name="VDDQ@4"/>
<pin name="DQ13"/>
<pin name="DQ14"/>
<pin name="VSSQ@4"/>
<pin name="DQ15"/>
<pin name="VSS@3"/>
</symbol>
<symbol name="DDR2">
<pin name="VDD@1"/>
<pin name="DQ6"/>
<pin name="VDDQ@1"/>
<pin name="DQ4"/>
<pin name="VDDL"/>
<pin name="BA2"/>
<pin name="VSS@1"/>
<pin name="VDD@2"/>
<pin name="NU/!RDQS"/>
<pin name="VSSQ@1"/>
<pin name="DQ1"/>
<pin name="VSSQ@2"/>
<pin name="VREF"/>
<pin name="CKE"/>
<pin name="BA0"/>
<pin name="A10/AP"/>
<pin name="A3"/>
<pin name="A7"/>
<pin name="A12"/>
<pin name="VSS@2"/>
<pin name="DM/RDQS"/>
<pin name="VDDQ@2"/>
<pin name="DQ3"/>
<pin name="VSS@3"/>
<pin name="!WE"/>
<pin name="BA1"/>
<pin name="A1"/>
<pin name="A5"/>
<pin name="A9"/>
<pin name="A14"/>
<pin name="VSSQ@3"/>
<pin name="DQS"/>
<pin name="VDDQ@3"/>
<pin name="DQ2"/>
<pin name="VSSDL"/>
<pin name="!RAS"/>
<pin name="!CAS"/>
<pin name="A2"/>
<pin name="A6"/>
<pin name="A11"/>
<pin name="!DQS"/>
<pin name="VSSQ@4"/>
<pin name="DQ0"/>
<pin name="VSSQ@5"/>
<pin name="CK"/>
<pin name="!CK"/>
<pin name="!CS"/>
<pin name="A0"/>
<pin name="A4"/>
<pin name="A8"/>
<pin name="A13"/>
<pin name="VDDQ@4"/>
<pin name="DQ5"/>
<pin name="VDD@3"/>
<pin name="ODT"/>
<pin name="VDD@4"/>
<pin name="VSS@4"/>
<pin name="DQ7"/>
<pin name="VDDQ@5"/>
</symbol>
<symbol name="DDR2X16">
<pin name="VDD@1"/>
<pin name="DQ14"/>
<pin name="VDDQ@1"/>
<pin name="DQ12"/>
<pin name="VDD@2"/>
<pin name="DQ6"/>
<pin name="VDDQ@2"/>
<pin name="DQ4"/>
<pin name="VDDL"/>
<pin name="BA2"/>
<pin name="VSS@1"/>
<pin name="VDD@3"/>
<pin name="VSSQ@1"/>
<pin name="DQ9"/>
<pin name="VSSQ@2"/>
<pin name="VSSQ@3"/>
<pin name="DQ1"/>
<pin name="VSSQ@4"/>
<pin name="VREF"/>
<pin name="CKE"/>
<pin name="BA0"/>
<pin name="A10"/>
<pin name="A3"/>
<pin name="A7"/>
<pin name="A12"/>
<pin name="VSS@2"/>
<pin name="UDM"/>
<pin name="VDDQ@3"/>
<pin name="DQ11"/>
<pin name="VSS@3"/>
<pin name="LDM"/>
<pin name="VDDQ@4"/>
<pin name="DQ3"/>
<pin name="VSS@4"/>
<pin name="!WE"/>
<pin name="BA1"/>
<pin name="A1"/>
<pin name="A5"/>
<pin name="A9"/>
<pin name="VSSQ@5"/>
<pin name="UDQS"/>
<pin name="VDDQ@5"/>
<pin name="DQ10"/>
<pin name="VSSQ@6"/>
<pin name="LDQS"/>
<pin name="VDDQ@6"/>
<pin name="DQ2"/>
<pin name="VSSDL"/>
<pin name="!RAS"/>
<pin name="!CAS"/>
<pin name="A2"/>
<pin name="A6"/>
<pin name="A11"/>
<pin name="!UDQS"/>
<pin name="VSSQ@7"/>
<pin name="DQ8"/>
<pin name="VSSQ@8"/>
<pin name="!LDQS"/>
<pin name="VSSQ@9"/>
<pin name="DQ0"/>
<pin name="VSSQ@10"/>
<pin name="CK"/>
<pin name="!CK"/>
<pin name="!CS"/>
<pin name="A0"/>
<pin name="A4"/>
<pin name="A8"/>
<pin name="VDDQ@7"/>
<pin name="DQ15"/>
<pin name="VDDQ@8"/>
<pin name="DQ13"/>
<pin name="VDDQ@9"/>
<pin name="DQ7"/>
<pin name="VDDQ@10"/>
<pin name="DQ5"/>
<pin name="VDD@4"/>
<pin name="ODT"/>
<pin name="VDD@5"/>
<pin name="VSS@5"/>
<pin name="A13"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="AS4C16M16SA" prefix="U">
<gates>
<gate name="G$1" symbol="SDRAM"/>
</gates>
<devices>
<device name="" package="TFBGA-54">
<connects>
<connect gate="G$1" pin="!CAS" pad="F7"/>
<connect gate="G$1" pin="!CS" pad="G9"/>
<connect gate="G$1" pin="!RAS" pad="F8"/>
<connect gate="G$1" pin="!WE" pad="F9"/>
<connect gate="G$1" pin="A0" pad="H7"/>
<connect gate="G$1" pin="A1" pad="H8"/>
<connect gate="G$1" pin="A10/AP" pad="H9"/>
<connect gate="G$1" pin="A11" pad="G2"/>
<connect gate="G$1" pin="A12" pad="G1"/>
<connect gate="G$1" pin="A2" pad="J8"/>
<connect gate="G$1" pin="A3" pad="J7"/>
<connect gate="G$1" pin="A4" pad="J3"/>
<connect gate="G$1" pin="A5" pad="J2"/>
<connect gate="G$1" pin="A6" pad="H3"/>
<connect gate="G$1" pin="A7" pad="H2"/>
<connect gate="G$1" pin="A8" pad="H1"/>
<connect gate="G$1" pin="A9" pad="G3"/>
<connect gate="G$1" pin="BA0" pad="G7"/>
<connect gate="G$1" pin="BA1" pad="G8"/>
<connect gate="G$1" pin="CKE" pad="F3"/>
<connect gate="G$1" pin="CLK" pad="F2"/>
<connect gate="G$1" pin="DQ0" pad="A8"/>
<connect gate="G$1" pin="DQ1" pad="B9"/>
<connect gate="G$1" pin="DQ10" pad="D1"/>
<connect gate="G$1" pin="DQ11" pad="C2"/>
<connect gate="G$1" pin="DQ12" pad="C1"/>
<connect gate="G$1" pin="DQ13" pad="B2"/>
<connect gate="G$1" pin="DQ14" pad="B1"/>
<connect gate="G$1" pin="DQ15" pad="A2"/>
<connect gate="G$1" pin="DQ2" pad="B8"/>
<connect gate="G$1" pin="DQ3" pad="C9"/>
<connect gate="G$1" pin="DQ4" pad="C8"/>
<connect gate="G$1" pin="DQ5" pad="D9"/>
<connect gate="G$1" pin="DQ6" pad="D8"/>
<connect gate="G$1" pin="DQ7" pad="E9"/>
<connect gate="G$1" pin="DQ8" pad="E1"/>
<connect gate="G$1" pin="DQ9" pad="D2"/>
<connect gate="G$1" pin="DQMH" pad="F1"/>
<connect gate="G$1" pin="DQML" pad="E8"/>
<connect gate="G$1" pin="VDD@1" pad="A9"/>
<connect gate="G$1" pin="VDD@2" pad="E7"/>
<connect gate="G$1" pin="VDD@3" pad="J9"/>
<connect gate="G$1" pin="VDDQ@1" pad="A7"/>
<connect gate="G$1" pin="VDDQ@2" pad="B3"/>
<connect gate="G$1" pin="VDDQ@3" pad="C7"/>
<connect gate="G$1" pin="VDDQ@4" pad="D3"/>
<connect gate="G$1" pin="VSS@1" pad="A1"/>
<connect gate="G$1" pin="VSS@2" pad="E3"/>
<connect gate="G$1" pin="VSS@3" pad="J1"/>
<connect gate="G$1" pin="VSSQ@1" pad="A3"/>
<connect gate="G$1" pin="VSSQ@2" pad="B7"/>
<connect gate="G$1" pin="VSSQ@3" pad="C3"/>
<connect gate="G$1" pin="VSSQ@4" pad="D7"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AS4C128M8D2" prefix="U">
<gates>
<gate name="G$1" symbol="DDR2"/>
</gates>
<devices>
<device name="-25BCN" package="TFBGA-60">
<connects>
<connect gate="G$1" pin="!CAS" pad="G7"/>
<connect gate="G$1" pin="!CK" pad="F7"/>
<connect gate="G$1" pin="!CS" pad="G8"/>
<connect gate="G$1" pin="!DQS" pad="A8"/>
<connect gate="G$1" pin="!RAS" pad="F6"/>
<connect gate="G$1" pin="!WE" pad="F3"/>
<connect gate="G$1" pin="A0" pad="H7"/>
<connect gate="G$1" pin="A1" pad="H3"/>
<connect gate="G$1" pin="A10/AP" pad="H2"/>
<connect gate="G$1" pin="A11" pad="K6"/>
<connect gate="G$1" pin="A12" pad="L2"/>
<connect gate="G$1" pin="A13" pad="L8"/>
<connect gate="G$1" pin="A14" pad="L3"/>
<connect gate="G$1" pin="A2" pad="H6"/>
<connect gate="G$1" pin="A3" pad="J2"/>
<connect gate="G$1" pin="A4" pad="J8"/>
<connect gate="G$1" pin="A5" pad="J3"/>
<connect gate="G$1" pin="A6" pad="J7"/>
<connect gate="G$1" pin="A7" pad="K2"/>
<connect gate="G$1" pin="A8" pad="K7"/>
<connect gate="G$1" pin="A9" pad="K3"/>
<connect gate="G$1" pin="BA0" pad="G2"/>
<connect gate="G$1" pin="BA1" pad="G3"/>
<connect gate="G$1" pin="BA2" pad="G1"/>
<connect gate="G$1" pin="CK" pad="E8"/>
<connect gate="G$1" pin="CKE" pad="F2"/>
<connect gate="G$1" pin="DM/RDQS" pad="B3"/>
<connect gate="G$1" pin="DQ0" pad="C8"/>
<connect gate="G$1" pin="DQ1" pad="C2"/>
<connect gate="G$1" pin="DQ2" pad="D7"/>
<connect gate="G$1" pin="DQ3" pad="D3"/>
<connect gate="G$1" pin="DQ4" pad="D1"/>
<connect gate="G$1" pin="DQ5" pad="D9"/>
<connect gate="G$1" pin="DQ6" pad="B1"/>
<connect gate="G$1" pin="DQ7" pad="B9"/>
<connect gate="G$1" pin="DQS" pad="B7"/>
<connect gate="G$1" pin="NU/!RDQS" pad="A2"/>
<connect gate="G$1" pin="ODT" pad="F8"/>
<connect gate="G$1" pin="VDD@1" pad="A1"/>
<connect gate="G$1" pin="VDD@2" pad="E9"/>
<connect gate="G$1" pin="VDD@3" pad="H8"/>
<connect gate="G$1" pin="VDD@4" pad="L1"/>
<connect gate="G$1" pin="VDDL" pad="E1"/>
<connect gate="G$1" pin="VDDQ@1" pad="A9"/>
<connect gate="G$1" pin="VDDQ@2" pad="C1"/>
<connect gate="G$1" pin="VDDQ@3" pad="C3"/>
<connect gate="G$1" pin="VDDQ@4" pad="C7"/>
<connect gate="G$1" pin="VDDQ@5" pad="C9"/>
<connect gate="G$1" pin="VREF" pad="E2"/>
<connect gate="G$1" pin="VSS@1" pad="A3"/>
<connect gate="G$1" pin="VSS@2" pad="E3"/>
<connect gate="G$1" pin="VSS@3" pad="J1"/>
<connect gate="G$1" pin="VSS@4" pad="K8"/>
<connect gate="G$1" pin="VSSDL" pad="E7"/>
<connect gate="G$1" pin="VSSQ@1" pad="A7"/>
<connect gate="G$1" pin="VSSQ@2" pad="B2"/>
<connect gate="G$1" pin="VSSQ@3" pad="B8"/>
<connect gate="G$1" pin="VSSQ@4" pad="D2"/>
<connect gate="G$1" pin="VSSQ@5" pad="D8"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AS4C64M16D2">
<gates>
<gate name="G$1" symbol="DDR2X16"/>
</gates>
<devices>
<device name="-25BCN" package="TFBGA-84">
<connects>
<connect gate="G$1" pin="!CAS" pad="L7"/>
<connect gate="G$1" pin="!CK" pad="K8"/>
<connect gate="G$1" pin="!CS" pad="L8"/>
<connect gate="G$1" pin="!LDQS" pad="E8"/>
<connect gate="G$1" pin="!RAS" pad="K7"/>
<connect gate="G$1" pin="!UDQS" pad="A8"/>
<connect gate="G$1" pin="!WE" pad="K3"/>
<connect gate="G$1" pin="A0" pad="M8"/>
<connect gate="G$1" pin="A1" pad="M3"/>
<connect gate="G$1" pin="A10" pad="M2"/>
<connect gate="G$1" pin="A11" pad="P7"/>
<connect gate="G$1" pin="A12" pad="R2"/>
<connect gate="G$1" pin="A13" pad="R8"/>
<connect gate="G$1" pin="A2" pad="M7"/>
<connect gate="G$1" pin="A3" pad="N2"/>
<connect gate="G$1" pin="A4" pad="N8"/>
<connect gate="G$1" pin="A5" pad="N3"/>
<connect gate="G$1" pin="A6" pad="N7"/>
<connect gate="G$1" pin="A7" pad="P2"/>
<connect gate="G$1" pin="A8" pad="P8"/>
<connect gate="G$1" pin="A9" pad="P3"/>
<connect gate="G$1" pin="BA0" pad="L2"/>
<connect gate="G$1" pin="BA1" pad="L3"/>
<connect gate="G$1" pin="BA2" pad="L1"/>
<connect gate="G$1" pin="CK" pad="J8"/>
<connect gate="G$1" pin="CKE" pad="K2"/>
<connect gate="G$1" pin="DQ0" pad="G8"/>
<connect gate="G$1" pin="DQ1" pad="G2"/>
<connect gate="G$1" pin="DQ10" pad="D7"/>
<connect gate="G$1" pin="DQ11" pad="D3"/>
<connect gate="G$1" pin="DQ12" pad="D1"/>
<connect gate="G$1" pin="DQ13" pad="D9"/>
<connect gate="G$1" pin="DQ14" pad="B1"/>
<connect gate="G$1" pin="DQ15" pad="C2"/>
<connect gate="G$1" pin="DQ2" pad="H7"/>
<connect gate="G$1" pin="DQ3" pad="H3"/>
<connect gate="G$1" pin="DQ4" pad="H1"/>
<connect gate="G$1" pin="DQ5" pad="H9"/>
<connect gate="G$1" pin="DQ6" pad="F1"/>
<connect gate="G$1" pin="DQ7" pad="F9"/>
<connect gate="G$1" pin="DQ8" pad="C8"/>
<connect gate="G$1" pin="DQ9" pad="B3"/>
<connect gate="G$1" pin="LDM" pad="F3"/>
<connect gate="G$1" pin="LDQS" pad="F7"/>
<connect gate="G$1" pin="ODT" pad="K9"/>
<connect gate="G$1" pin="UDM" pad="B8"/>
<connect gate="G$1" pin="UDQS" pad="B9"/>
<connect gate="G$1" pin="VDD@1" pad="A1"/>
<connect gate="G$1" pin="VDD@2" pad="E1"/>
<connect gate="G$1" pin="VDD@3" pad="J9"/>
<connect gate="G$1" pin="VDD@4" pad="M9"/>
<connect gate="G$1" pin="VDD@5" pad="R1"/>
<connect gate="G$1" pin="VDDL" pad="J1"/>
<connect gate="G$1" pin="VDDQ@1" pad="A9"/>
<connect gate="G$1" pin="VDDQ@10" pad="C1"/>
<connect gate="G$1" pin="VDDQ@2" pad="C3"/>
<connect gate="G$1" pin="VDDQ@3" pad="C7"/>
<connect gate="G$1" pin="VDDQ@4" pad="C9"/>
<connect gate="G$1" pin="VDDQ@5" pad="E9"/>
<connect gate="G$1" pin="VDDQ@6" pad="G1"/>
<connect gate="G$1" pin="VDDQ@7" pad="G3"/>
<connect gate="G$1" pin="VDDQ@8" pad="G7"/>
<connect gate="G$1" pin="VDDQ@9" pad="G9"/>
<connect gate="G$1" pin="VREF" pad="J2"/>
<connect gate="G$1" pin="VSS@1" pad="A3"/>
<connect gate="G$1" pin="VSS@2" pad="E3"/>
<connect gate="G$1" pin="VSS@3" pad="J3"/>
<connect gate="G$1" pin="VSS@4" pad="N1"/>
<connect gate="G$1" pin="VSS@5" pad="P9"/>
<connect gate="G$1" pin="VSSDL" pad="J7"/>
<connect gate="G$1" pin="VSSQ@1" pad="A7"/>
<connect gate="G$1" pin="VSSQ@10" pad="H8"/>
<connect gate="G$1" pin="VSSQ@2" pad="B2"/>
<connect gate="G$1" pin="VSSQ@3" pad="B7"/>
<connect gate="G$1" pin="VSSQ@4" pad="E7"/>
<connect gate="G$1" pin="VSSQ@5" pad="D2"/>
<connect gate="G$1" pin="VSSQ@6" pad="D8"/>
<connect gate="G$1" pin="VSSQ@7" pad="F2"/>
<connect gate="G$1" pin="VSSQ@8" pad="F8"/>
<connect gate="G$1" pin="VSSQ@9" pad="H2"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
